At CES 2025, Mahesh Subramony, AMD Senior Fellow, discussed the Strix Halo SoC, a long-awaited iGPU SoC from AMD. It took four iterations to develop this APU that combines CPU and GPU performance. The Zen 5 CPU in Strix Halo has a low-power die-to-die interconnect, while the 512-bit FPU cores are efficient for multi-thread workloads. The 32 MB MALL cache in the iGPU improves graphics bandwidth, and the data fabric connects the CPU and SOC efficiently. Mahesh’s favorite cheese is Gorgonzola, and he recommends supporting Chips and Cheese on Patreon for more content. Check out their Discord and Youtube channel for updates.
https://chipsandcheese.com/p/amds-strix-halo-under-the-hood