In this study, we introduce an extension of the Karatsuba algorithm to matrix multiplication, aiming to reduce complexity while maintaining efficiency. Our proposed algorithm and hardware architectures show improvements in area and execution time for integer matrix multiplication compared to traditional methods. The designs support implementation through proven systolic array and conventional multiplier architectures, proving beneficial for deep learning accelerators. Our analysis highlights the enhanced performance-per-area of the proposed approach, marking a significant advancement in the field. This innovative extension challenges conventional norms, offering a promising solution for optimizing matrix multiplication in custom hardware setups.
https://arxiv.org/abs/2501.08889