The Verilog to Routing (VTR) project offers open-source CAD tools for FPGA architecture and CAD research. Users are free to use, modify, and distribute the software under the MIT license. This allows for the exploration of new FPGA architectures and CAD algorithms that closed-source tools may not permit. The VTR design flow involves several steps, including elaboration and synthesis, logic optimization and technology mapping, as well as packing, placement, routing, and timing analysis. VTR can generate FPGA speed and area results and provide information for bitstream generation. It is compatible with a range of hypothetical, commercial-like, and commercial FPGA architectures and offers benchmark designs for evaluation purposes. More information can be found in the documentation.
https://verilogtorouting.org/