The author dissects a military-grade chip from IDT with surprising findings: a layout of over 1500 transistors but less than 20% are used, forming scattered circuits. The chip implements a “1-of-4” decoder function with intricate gates and surroundings of unused transistors. The construction details of both NAND and NOR gates are explained, showcasing the chip’s complex logic structure. The author explores the history of logic integrated circuits leading to the 7400 series and examines the efficiency of gate array designs for certain markets like high-performance and military applications. The unique packaging of the chip on a multi-chip module with Atmel EEPROMs adds further intrigue to the analysis.
https://www.righto.com/2024/03/idt-gate-array.html