JEDEC introduced the DDR5 specification in 2020, and now they’re ready for an upgrade with the DDR5-8800 specification. The new DDR5-8800 has loose CL62 62-62 timings for A-grade devices and CL78 77-77 for C-grade ICs. The standard aims at improving peak memory bandwidth by 37.5%. The security front has also been addressed with the Per-Row Activation Counting feature, designed to counter rowhammer-style exploits. Notably, the DDR5 specification discontinues support for Partial Array Self Refresh for security reasons. While extreme overclockers are already pushing the limits of current DDR5 chips, the new spec offers potential for even higher speeds.
https://www.anandtech.com/show/21363/jedec-extends-ddr5-specification-to-8800-mts-adds-anti-rowhammer-features