ARM’s Neoverse N2: Cortex A710 for Servers

ARM’s Neoverse N2 is a continuation of the success of its previous server chip, Neoverse N1. Neoverse N2, featured in Alibaba’s Yitian 710 cloud instance, has 128 cores running at 2.75 GHz and boasts 60 billion transistors. The architecture of N2 is similar to ARM’s Cortex A710 and competes with AMD’s Zen 4. N2 has a 10-cycle pipeline and a branch predictor that is slightly behind Zen 4’s. In terms of execution, N2 has a good scheduling capacity and execution throughput, but could use more register file and ROB capacity. N2 and Zen 4 both introduce vector extensions and support larger memory footprints. N2 has a 48-bit physical addressing support, while Zen 4 supports up to 52-bit physical addressing. N2’s cache configuration includes a 64 KB L1 cache, optional hardware instruction cache coherency, and a recommended 1 MB L2 cache. Its L3 cache, connected via the CMN-700 mesh interconnect, suffers from high latency. N2’s DDR5 performance is also impacted by high DRAM latency. In terms of shared cache bandwidth, N

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