Chisel is an open-source hardware description language (HDL) that allows designers to describe digital electronics and circuits at the register-transfer level. It adds hardware construction primitives to the Scala programming language, enabling designers to write complex circuit generators that produce synthesizable Verilog. Chisel promotes the creation of re-usable components and libraries, offering a higher level of abstraction in design while maintaining control. Chisel is powered by FIRRTL, a hardware compiler framework implemented by LLVM CIRCT. It is permissively licensed under the guidance of CHIPS Alliance. Chisel provides various resources and tutorials for users and contributors to get started with the language and design projects.
https://github.com/chipsalliance/chisel