In the world of out-of-order microarchitectures, execution units don’t necessarily stay occupied until the task is complete, as seen in the Firestorm microarchitecture of A14 and M1 chips. Despite initial assumptions, many microarchitectures are heavily pipelined, allowing for multiple tasks to be processed simultaneously. This means that a sequence of instructions like multiplies can be executed more efficiently than thought. This revelation sheds light on how instruction latency and bandwidth are specified in tables, ultimately affecting cycles per instruction. For a deeper dive into this concept, check out Luna Razzaghipour’s GitHub repo with hands-on examples to understand the complexities of microarchitectures.
https://blog.xoria.org/pipelining/