This detailed web content explores Z80 instruction timings using a Z80 netlist simulation. It covers general instruction timing, M-cycles, T-states, and various machine cycles like Opcode Fetch, Memory Read, Memory Write, and more. The Z80 instruction set is complex due to its need to be binary compatible with the Intel 8080, resulting in a mix of structured and random instructions. The Z80 emulator created by the author offers improved performance and a unique tracelog feature for simulation analysis. The article also delves into the historical context of Z80 development and the differences from original Z80s. The blog post is part one of a series discussing this new emulator.
https://floooh.github.io/2021/12/06/z80-instruction-timing.html#table-of-content