Intel, Samsung, and TSMC Demo 3D-Stacked Transistors

At the IEEE International Electron Devices Meeting, Intel, Samsung, and TSMC showcased their progress in developing CFETS (complementary field-effect transistors), which could lead to processors with almost double the density of transistors. CFETs involve stacking different types of transistors needed for CMOS logic into a single structure. The transition from FinFET to nanosheet transistors is underway, with CFETs expected to be commercially available in seven to ten years. Intel demonstrated an inverter circuit using CFETs that was 50% the size of a traditional CMOS inverter. Samsung achieved smaller contacted poly pitch (CPP) sizes, while TSMC focused on isolating the two stacked devices using an innovative dielectric layer.

https://spectrum.ieee.org/cfet-intel-samsung-tsmc

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