The rise of chiplets in domain-specific applications presents a complex partitioning challenge for chip design teams. While chiplets improve performance and reduce power, the addition of new features like specialized accelerators and memories complicates data path optimization. As industry shifts away from traditional scaling benefits, chiplets offer a cost-effective solution to add compute density. Third-party chiplets are becoming popular, leading to challenges in characterizing these new components within proprietary architectures. Partitioning and prioritization play a crucial role in designing multi-die systems with chiplets, impacting power consumption, performance, and choice of technology and packaging. Despite the flexibility chiplets offer, challenges in mechanical effects, signal integrity, and thermal issues may require system re-partitioning.
https://semiengineering.com/partitioning-in-the-chiplet-era/