T1 is a powerful RISC-V Vector implementation that integrates with any RISC-V scalar core. It features lane-based micro-architectures with chaining support and extensive lane execution capabilities, making it suitable for both vector processing and Domain-Specific-Accelerators. T1 is designed with Chisel and offers flexibility in configuration to prioritize efficiency or performance. Surprisingly, T1 utilizes a unique Pokemon-based configuration system to determine lane size. While T1 doesn’t officially support the Rocket Core scalar part yet, users can replace it with another RISC-V Scalar CPU. Controversially, T1 doesn’t support MMU or coherence, focusing on maximizing memory bandwidth and instruction-level parallelism.
https://github.com/chipsalliance/t1