TSMC unveiled its groundbreaking 2nm Platform Technology at IEDM 2024, showcasing energy-efficient nanosheet transistors and 3DIC co-optimization for various applications. The 2nm process boasts a 30% power improvement and 15% performance gain compared to their previous 3nm node, making it the most power-efficient in its class. While the paper lacked technical details typically seen at IEDM, it painted a picture of a process ready for 2025 production. TSMC’s 2nm power improvement surpasses Samsung’s, and although pricing at $30,000 per wafer is high, it could open opportunities for Intel and Samsung. The implementation of backside power delivery and flat passivation adds unique elements to TSMC’s 2nm process.
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