TSMC unveiled its latest 1.6nm-class A16 manufacturing process, featuring the innovative Super Power Rail (SPR) backside power delivery network. This technology promises up to 10% higher clock rates and 15-20% lower power consumption compared to its predecessor, N2P. The SPR implementation is complex but offers improved performance and power efficiency, particularly for AI and HPC processors. TSMC’s decision to offer both 1.6nm-class and 2nm-class nodes with different transistor designs avoids direct competition but provides unique advantages for customers. Volume production of A16 is set to start in the second half of 2026, with product availability expected in 2027, potentially posing a challenge to Intel’s 14A node.
https://www.tomshardware.com/tech-industry/tsmc-unveils-16nm-process-technology-with-backside-power-delivery-rivals-intels-competing-design