Veryl is a modern hardware description language positioned as a “SystemVerilog Alternative.” It offers simplified syntax, SystemVerilog/Rust-based design, and removes traditional Verilog syntax. Notably, it transpiles to SystemVerilog, generates readable code, and promotes interoperability with SystemVerilog. The language boasts integrated tools like a formatter and linter, with support for VSCode and vim/neovim. Veryl allows for package management based on git and supports localparam and logic declarations. For installation, usage instructions, and licensing details, refer to the documentation. Contributions to the project are welcomed under Apache License 2.0 or MIT license options.
https://github.com/veryl-lang/veryl