The recent Request for Startups from YC has garnered attention in chip design communities, as they propose using large language models (LLMs) to significantly reduce the cost of chip design and make hardware acceleration more feasible. However, critics argue that LLMs, despite being able to write functional code, are not capable of designing innovative chip architectures essential for performance improvements. While LLMs may have some value in niche markets like genomics and CFD workloads, leveraging them for mainstream chips may not be economically viable. Instead, LLMs could be more useful in speeding up chip verification processes, addressing the talent shortage in the verification sector. Ultimately, LLMs will make chip design cheaper, benefiting large semiconductor companies, conventional chip startups, and EDA software startups.
https://www.zach.be/p/yc-is-wrong-about-llms-for-chip-design